LM2512 Datasheet | National Semiconductor

Description The LM2512 is a MPL Serializer (SER) that performs a 24-bit to 18-bit Dither operation and serialization of the video signals to Mobile Pixel link (MPL) levels on only 3 or 4 active signals. An optional Look Up Table (Three X 256 X 8 bit RAM) is also provided for independent color correction. 18-bit Bufferless or partial buffer displays from QVGA (320 x 240) up to VGA (640 x 480) pixels can utilize a 24-bit video source. The interconnect is reduced from 28 signals to only 3 or 4 active signals with the LM2512 and panion deserializer easing flex interconnect design, size constraints and cost. The LM2512 SER resides by the application, graphics or baseband processor and translates the wide parallel video bus from LVCMOS levels to serial Mobile Pixel Link levels for transmission over a flex cable (or coax) and PCB traces to the DES located near or in the display module. When in Power_Down, the SER is put to sleep and draws less than 10μA. The link can also be powered down by stopping the PCLK (DES dependant) or by the PD- input pins. The LM2512 implements the physical layer of the MPL Level 0 Standard (MPL-0) and a 450 μA IOMS current (Class 0). Features - 24-bit RGB Display Interface support up to 640 x 480 VGA formats 24 to 18-bit Dithering Optional Look Up Table for independent color correction MPL-Level 0 Physical Layer SPI Interface for Look Up Table control and loading Low Power Consumption & Powerdown state Level translation between host and display Optional Auto Power Down on STOP PCLK Frame Sequence bits automatically resync upon data or clock error - 1.6V to 2.0V core / analog supply voltage - 1.6V to 3.0V I/O supply voltage range - - - - - - - - System Benefits - - - - - - - Dithered Data Reduction Independent RGB Color Correction 24-bit Color Input Small Interface Low Power Low EMI Intrinsic Level Translation Typical 3 MD Lane Application Diagram - Bridge Chip Ordering Information NSID LM2512SM LM2512SN Package Type 49L UFBGA,...