MM74HC533 Datasheet | National Semiconductor

Description These high speed OCTAL D-TYPE LATCHES utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power consumption of standard CMOS integrated circuits as well as the ability to drive 15 LS-TTL loads Due to the large output drive capability and the TRI-STATE feature these devices are ideally suited for interfacing with bus lines in a bus organized system When the LATCH ENABLE input is high the data present on the D inputs will appear inverted at the Q outputs When the LATCH ENABLE goes low the inverted data will be retained at the Q outputs until LATCH ENABLE returns high again When a high logic level is applied to the OUTPUT CONTROL input all outputs go to a high impedance state regardless of what signals are present at the other inputs and the state of the storage elements The 54HC 74HC logic family is speed function and pin-out patible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground Features Y Typical propagation delay 18 ns Y Wide operating voltage range 2 to 6 volts Y Low input current 1 m A maximum Y Low quiescent current 80 m A maximum (74HC Series) Y patible with bus-oriented systems Y Output drive capability 15 LS-TTL loads Connection Diagram Dual-In-Line Package Truth Table Output Control Top View Order Number MM54HC533 or MM74HC533 TL F 5339 - 1 Latch Enable Data Output L H Q0 Z H e high level L e low level Q0 e level of output before steady-state input conditions were established Z e high impedance TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 5339 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) DC Input Voltage (VIN)...