MM74HC595 Datasheet | National Semiconductor

MM54HC595 MM74HC595 8-Bit Shift Registers with Output Latches January 1988 MM54HC595 MM74HC595 8-Bit Shift Registers with Output Latches General Description This high speed shift register utilizes advanced silicon-gate CMOS technology This device possesses the high noise immunity and low power consumption of standard CMOS integrated circuits as well as the ability to drive 15 LS-TTL loads This device contains an 8-bit serial-in parallel-out shift register that feeds an 8-bit D-type storage register The storage register has 8 TRI-STATE outputs Separate clocks are provided for both the shift register and the storage register The shift register has a direct-overriding clear serial input and serial output (standard) pins for cascading Both the shift register and storage register use positive-edge triggered clocks If both clocks are connected together the shift register state will always be one clock pulse ahead of the storage register The 54HC 74HC logic family is speed function and pin-out patible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground Connection Diagram Features Y Low quiescent current 80 m A maximum (74HC Series) Y Low input current 1 m A maximum Y 8-bit serial-in parallel-out shift register with storage Y Wide operating voltage range 2V - 6V Y Cascadable Y Shift register has direct clear Y Guaranteed shift frequency DC to 30 MHz Truth Table Dual-In-Line Package RCK SCK SCLR G Function Xu u X H QA thru QHe TRI STATE L Shift Register cleared Q He L Shift Register clocked QNe Qn Q e SER L Contents of Shift Register transferred to output latches Top View TL F 5342 - 1 Order Number MM54HC595 or MM74HC595 TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 5342 RRD-B30M105 Printed in U S...