NS16550A Datasheet | National Semiconductor

overview of the PS 2 system board and Micro Channel Architecture (MCA) in the Models 50 60 70 and 80 personal puters The next part explains the basic configuration and system initialization procedures for the UART that occur after power-up The last part describes the overall interrupt procedure and the advantages of using the on-chip FIFOs of the NS16550A These explanations describe the CPU accesses to the UART via MCA Timing diagrams in the appendix show these accesses to the UART OVERVIEW OF THE PS 2 MODEL 50 60 70 AND 80 SYSTEM ARCHITECTURE The block diagram indicates a number of identical functions that all system boards have (Figure 1) Each system CPU has an 8 channel DMA Controller and an optional math coprocessor associated with it via the local bus The DMA Controller emulates the dual 8237 DMA controllers found on the IBM AT Additionally this DMA Controller provides Extended and Virtual Mode operation These modes allow it to interface with various DMA slave devices and the CPU to dynamically select the arbitration level for 2 of the DMA channels A central arbitration point allows certain adapter cards and system peripherals to pete for DMA transfers These adapter cards must have the appropriate arbitration and DMA logic Buffers condition the bus signals from the system CPU and send them directly to the Micro Channel Interface These signals after further buffering reach the system memory and the system peripherals The system ROM on the Models 50 and 60 also interfaces via these buffers to the 80286 CPU In the Models 70 and 80 the 128 kbyte ROM interfaces via the local bus to the 80386 CPU The dynamic RAM is expandable on the system board or on adapter cards DMA controller addressing capability limits the total DRAM available on any of these systems to 16 Mbytes The maximum DRAM available on the various system boards is 1 Model 50 Type 1 e 1 Mbyte Type 2 e 2 Mbytes 2 Model 60 e 1 Mbyte 3 Model 70 Type 1 or Type 2 e 6 Mbytes 4 Model 80 Type 1 e 2 Mbytes Type 2...