SCAN90CP02 Datasheet | National Semiconductor

Description The SCAN90CP02 is a 1.5 Gbps 2 x 2 LVDS crosspoint switch. High speed data paths and flow-through pinout minimize internal device jitter, while configurable 0/25/50/100% pre-emphasis overes external ISI jitter effects of lossy backplanes and cables. The differential inputs interface to LVDS and Bus LVDS signals such as those on National's 10-, 16-, and 18- bit Bus LVDS Ser Des, as well as CML and LVPECL. The SCAN90CP02 can also be used with ASICs and FPGAs. The non-blocking crosspoint architecture is pinconfigurable as a 1:2 clock or data splitter, 2:1 redundancy mux, crossover function, or dual buffer for signal booster and stub hider applications. Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports testability of both single-ended LVTTL/CMOS and differential LVDS PCB interconnect. The 3.3V supply, CMOS process, and LVDS I/O ensure high performance at low power over the entire industrial -40 to +85°C temperature range. Features - 1.5 Gbps per channel - Low power: 70 m A in dual repeater mode @1.5 Gbps - Low output jitter - Configurable 0/25/50/100% pre-emphasis drives lossy backplanes and cables - Non-blocking architecture allows 1:2 splitter, 2:1 mux, crossover, and dual buffer configurations - Flow-through pinout - LVDS/BLVDS/CML/LVPECL inputs, LVDS Outputs - IEEE 1149.1 and 1149.6 pliant - Single 3.3V supply - Separate control of inputs and outputs allows for power savings - Industrial -40 to +85°C temperature range - 28-lead LLP package, or 32-lead LQFP package Block Diagram FIGURE 1. SCAN90CP02 Block Diagram © 2007 National Semiconductor Corporation 200714 .national. Pin Descriptions Pin Name LLP Pin LQFP Number Pin Number I/O, Type Description DIFFERENTIAL INPUTS MON TO ALL MUXES IN0+ IN0- I, LVDS Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL patible. IN1+ IN1-...