DS3647A Datasheet | National Semiconductor

Description The DS3647A is a 4-bit I O buffer register intended for use in MOS memory systems This circuit employs a fall-through latch for data storage This method of latching captures the data in parallel with the output thus eliminating the delays encountered in other designs This circuit uses Schottkyclamped transistor logic for minimum propagation delay and employs PNP input transistors so that input currents are low allowing a large fan-out for this circuit which is needed in a memory system Two pins per bit are provided and data transfer is bi-directional so that the register can handle both input and output data The direction of data flow is controlled through the input enables The latch control when taken low will cause the register to hold the data present at that time and display it at the outputs Data can be latched into the register independent of the output disables or EXPANSION input Either or both of the outputs may be taken to the high-impedance state with the output disables The EXPANSION pin disables both outputs to facilitate multiplexing with other I O registers on the same data lines The DS3647A features TRI-STATE outputs The ‘‘B’’ port outputs are designed for use in bus organized data transmission systems and can sink 80 m A and source b5 2 m A Data going from port ‘‘A’’ to port ‘‘B’’ and from ‘‘B’’ to port ‘‘A’’ is inverted in the DS3647A Features Y Y Y Y Y Y Y Y PNP inputs minimize loading Fall-through latch design Propagation delay of only 15 ns TRI-STATE outputs EXPANSION control Bi-directional data flow TTL patible Transmission line driver output Logic and Connection Diagrams Dual-In-Line Package TL F 8354 - 2 Top View Order Number DS3647AD or DS3647AN See NS Package Number D16C or N16A TL F 8354 - 1 TRI-STATE is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation TL F 8354 RRD-B30M105 Printed in U S A .. Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are...