80C85AHRS Datasheet | OKI Electric

DESCRIPTION The MSM80C85AH is a plete 8-bit parallel; central processor implemented in silicon gate C-MOS technology and patible with MSM80C85A. It is designed with higher processing speed (max.5 MHz) and lower power consumption pared with MSM80C85A and power down mode is provided, thereby offering a high level of system integration. .. The MSM80C85AH uses a multiplexed address/data bus. The address is split between the 8bit address bus and the 8-bit data bus. The on-chip address latch : of a MSM81C55-5 memory product allows a direct interface with the MSM80C85AH. FEATURES - Power down mode (HALT-HOLD) - Low Power Dissipation: 50m W(Typ) - Single + 3 to + 6 V Power Supply - - 40 to + 85°C, Operating Temperature - patible with MSM80C85A - 0.8 ms instruction Cycle (VCC = 5V) - On-Chip Clock Generator (with External Crystal) - On-Chip System Controller; Advanced Cycle Status Information Available for Large System Control - Bug operation in MSM80C85AH is fixed - Four Vectored interrupt (One is non-maskable) Plus the 8080A-patible interrupt. - Serial, In/Serial Out Port - Decimal, Binary and Double Precision Arithmetic - Addressing Capability to 64K Bytes of Memory - TTL patible - 40-pin Plastic DIP(DIP40-P-600-2.54): (Product name: MSM80C85AHRS) - 44-pin Plastic QFJ(QFJ44-P-S650-1.27): (Product name: MSM80C85AHJS) - 44-pin Plastic QFP(QFP44-P-910-0.80-2K): (Product name: MSM80C85AHGS-2K) 1/29 ¡ Semiconductor MSM80C85AHRS/GS/JS FUNCTIONAL BLOCK DIAGRAM RST INTR INTA 5.5 6.5 7.5 TRAP SID SOD Interrupt Control Serial I/O Control 8-Bit Internal Data Bus .. Accumulator (8) Temporary Register (8) Flag (5) Flip Flops Instruction Register (8) Arithmetic Logic Unit ALU(8) Instruction Decoder And Machine Cycle Encoding B REG (8) D REG (8) H REG (8) C REG (8) E REG (8) C REG (8) Register Array Stack Pointer (16) Program Counter (16) Incrementer/Decrementer Address Latch (16) Power Supply +5V...