MC100E156 Overview
The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs.
MC100E156 Key Features
- For additional marking information, refer to Application Note AND8002/D
- For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering
- Rev. 8
- All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to
- D3x SEL0, SEL1 LEN1, LEN2 Q0
- Q2, Q0
- Q2 MR VCC, VCCO VEE FUNCTION ECL Input Data ECL Select Data ECL Latch Enables ECL Differential Outputs ECL Master Reset
