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MC100EP809 - Differential HSTL/PECL to HSTL Clock Driver

Description

designed with clock distribution in mind, accepting two clock sources into an input multiplexer.

Features

  • 100 ps Typical Device.
  • to.
  • Device Skew.
  • 15 ps Typical within Device Skew.
  • HSTL Compatible Outputs Drive 50 W to GND with no Offset Voltage.
  • Maximum Frequency > 750 MHz.
  • 850 ps Typical Propagation Delay.
  • Fully Compatible with Micrel SY89809L.
  • PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V.
  • Open Input Default State.
  • This Device is Pb.
  • Free and is RoH.

📥 Download Datasheet

Datasheet Details

Part number MC100EP809
Manufacturer onsemi
File Size 270.50 KB
Description Differential HSTL/PECL to HSTL Clock Driver
Datasheet download datasheet MC100EP809 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
3.3 V 2:1:9 Differential HSTL/PECL/LVDS to HSTL Clock Driver with LVTTL Clock Select and Enable MC100EP809 Description The MC100EP809 is a low skew 2:1:9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are one differential HSTL and one differential LVPECL. Both input pairs can accept LVDS levels. They are selected by the CLK_SEL pin which is LVTTL.
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