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MC100LVEL30 - Triple D Flip-Flop

General Description

differential outputs.

Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input.

Key Features

  • 1200 MHz Minimum Toggle Frequency.
  • 450 ps Typical Propagation Delays.
  • ESD Protection: > 2 kV Human Body Model.
  • The 100 Series Contains Temperature Compensation.
  • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V.
  • NECL Mode Operating Range: VCC = 0 V with VEE =.
  • 3.0 V to.
  • 3.8 V.
  • Internal Input 75 kW Pulldown Resistors.
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test.
  • Moisture Sens.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MC100LVEL30 3.3 V ECL Triple D Flip‐Flop with Set and Reset Description The MC100LVEL30 is a triple master-slave D flip-flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input. In addition to a common Set input individual Reset inputs are provided for each flip-flop. Both the Set and Reset inputs function asynchronous and overriding with respect to the clock inputs. Features • 1200 MHz Minimum Toggle Frequency • 450 ps Typical Propagation Delays • ESD Protection: > 2 kV Human Body Model • The 100 Series Contains Temperature Compensation. • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.