MC100LVEL37 Overview
SEMICONDUCTOR TECHNICAL DATA Product Preview ÷ ÷1:4 1/ 2 ECL/PECL Clock The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE, The D input will bias around VCC/2 and the Q output will go LOW. • Differential Inputs and Outputs • 20–Lead SOIC Packaging • 700ps Typical Propagation Delays • 50ps Output–Output Skews • Low Voltage 100K ECL • >2000V ESD Protection Figure 1. 20–Lead Pinout (Top View) MC100LVEL
