MC100LVEL39 Overview
MC100LVEL39 3.3 V ECL ÷2/4, ÷4/6 Clock Generation Chip The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the mon output edges are all precisely aligned. The device can be driven by either a differential or single-ended input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled...
MC100LVEL39 Key Features
- 50 ps Maximum Output-to-Output Skew
- Synchronous Enable/Disable
- Master Reset for Synchronization
- ESD Protection: Human Body Model; > 2 kV
- The 100 Series Contains Temperature pensation
- PECL Mode Operating Range
- NECL Mode Operating Range
- Internal Input Pulldown Resistors
- Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
- Moisture Sensitivity: Level 3 (Pb-Free)
MC100LVEL39 Applications
- 50 ps Maximum Output-to-Output Skew
