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MC74AC163 - Synchronous Presettable Binary Counter

Download the MC74AC163 datasheet PDF. This datasheet also covers the MC74ACT161 variant, as both devices belong to the same synchronous presettable binary counter family and are provided as variant models within a single manufacturer datasheet.

General Description

The MC74AC161/ACT161 and MC74AC163/ACT163 count modulo

16 binary sequence.

From state 15 (HHHH) they increment to state 0 (LLLL).

flops are driven in parallel through a clock buffer.

Key Features

  • Synchronous Counting and Loading.
  • High.
  • Speed Synchronous Expansion.
  • Typical Count Rate of 125 MHz.
  • Outputs Source/Sink 24 mA.
  • ′ACT161 and ′ACT163 Have TTL Compatible Inputs.
  • These are Pb.
  • Free Devices VCC TC Q0 Q1 Q2 Q3 CET PE 16 15 14 13 12 11 10 9 www. onsemi. com 16 1 xxx y A WL Y WW G.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MC74ACT161_ONSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number MC74AC163
Manufacturer onsemi
File Size 107.50 KB
Description Synchronous Presettable Binary Counter
Datasheet download datasheet MC74AC163 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163 Synchronous Presettable Binary Counter The MC74AC161/74ACT161 and MC74AC163/74ACT163 are high−speed synchronous modulo−16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74AC161/74ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The MC74AC163/74ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock.