Datasheet4U Logo Datasheet4U.com

MM74HC175 - Quad D-Type Flip-Flop

General Description

The MM74HC175 high speed D type flip flop with complementary outputs utilizes advanced silicon gate CMOS technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS

TTL loads.

Key Features

  • Typical Propagation Delay: 15 ns.
  • Wide Operating Supply Voltage Range: 2.
  • 6 V.
  • Low Input Current: 1 mA Maximum.
  • Low Quiescent Supply Current: 160 mA Maximum (74HC).
  • High Output Drive Current: 4 mA Minimum (74HC).
  • These are Pb.
  • Free Devices DATA SHEET www. onsemi. com 1 SOIC.
  • 16 CASE 751B 1 TSSOP.
  • 16 CASE 948F.

📥 Download Datasheet

Datasheet Details

Part number MM74HC175
Manufacturer onsemi
File Size 239.92 KB
Description Quad D-Type Flip-Flop
Datasheet download datasheet MM74HC175 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
MM74HC175 Quad D-Type Flip-Flop Fairchild
MM74HC174 Hex D Flip-Flops National Semiconductor
MM74HC174 Hex D-Type Flip-Flops with Clear Fairchild
MM74HC11 Triple 3-Input AND Gate National
MM74HC112 Dual J-K Flip-Flop National Semiconductor

Other Datasheets by onsemi

Part Number Description
MM74HC125 3-STATE Quad Buffers
MM74HC126 3-STATE Quad Buffers
MM74HC132 Quad 2-Input NAND Schmitt Trigger
MM74HC00 Quad 2-Input NAND Gate
MM74HC02 Quad 2-Input NOR Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Quad D-Type Flip-Flop With Clear MM74HC175 Description The MM74HC175 high speed D−type flip−flop with complementary outputs utilizes advanced silicon−gate CMOS technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS−TTL loads. Information at the D inputs of the MM74HC175 is transferred to the Q and Q outputs on the positive going edge of the clock pulse. Both true and complement outputs from each flip flop are externally available. All four flip−flops are controlled by a common clock and a common CLEAR. Clearing is accomplished by a negative pulse at the CLEAR input. All four Q outputs are cleared to a logical “0” and all four Q outputs to a logical “1.