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MTB3N100E - High Energy Power FET

Key Features

  • dds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductanc.

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Datasheet Details

Part number MTB3N100E
Manufacturer onsemi
File Size 276.02 KB
Description High Energy Power FET
Datasheet download datasheet MTB3N100E Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MTB3N100E Designer’s™ Data Sheet TMOS E−FET.™ High Energy Power FET D2PAK for Surface Mount N−Channel Enhancement−Mode Silicon Gate http://onsemi.com TMOS POWER FET The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage−blocking capability without degrading performance over time. In addition, this advanced TMOS E−FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain−to−source diode with a fast recovery time.