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NBC12430A - Programmable PLL Synthesized Clock Generator

This page provides the datasheet information for the NBC12430A, a member of the NBC12430 Programmable PLL Synthesized Clock Generator family.

Description

of the functionality of the NBC12430 and NBC12430A Inputs and Outputs.

explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors.

The PECL outputs are capable of driving two series terminated 50 W transmission lines on the incident edge.

Features

  • Best.
  • in.
  • Class Output Jitter Performance, ±20 ps Peak.
  • to.
  • Peak.
  • 50 MHz to 800 MHz Programmable Differential PECL Outputs.
  • Fully Integrated Phase.
  • Lock.
  • Loop with Internal Loop Filter.
  • Parallel Interface for Programming Counter and Output Dividers During Powerup.
  • Minimal Frequency Overshoot.
  • Serial 3.
  • Wire Programming Interface.
  • Crystal Oscillator Interface.
  • Operating Range:.

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Datasheet preview – NBC12430A

Datasheet Details

Part number NBC12430A
Manufacturer ON Semiconductor
File Size 344.39 KB
Description Programmable PLL Synthesized Clock Generator
Datasheet download datasheet NBC12430A Datasheet
Additional preview pages of the NBC12430A datasheet.

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Full PDF Text Transcription

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3.3 V/5 V Programmable PLL Synthesized Clock Generator 50 MHz to 800 MHz NBC12430, NBC12430A The NBC12430 and NBC12430A are general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The VCO frequency is sent to the N−output divider, where it can be configured to provide division ratios of 1, 2, 4, or 8. The VCO and output frequency can be programmed using the parallel or serial interfaces to the configuration logic. Output frequency steps of 250 kHz, 500 kHz, 1.0 MHz, 2.0 MHz can be achieved using a 16 MHz crystal, depending on the output dividers settings. The PLL loop filter is fully integrated and does not require any external components.
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