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NL17SHT126 - Noninverting Buffer / CMOS Logic Level Shifter

Datasheet Summary

Features

  • High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V.
  • Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C.
  • TTL.
  • Compatible Inputs: VIL = 0.8 V; VIH = 2 V.
  • CMOS.
  • Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load.
  • Power Down Protection Provided on Inputs and Outputs.
  • Balanced Propagation Delays.
  • Pin and Function Compatible with Other Standard Logic Families.
  • These are Pb.
  • Free Devices IN A 1 GND 2 OE 3 5 V.

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Datasheet Details

Part number NL17SHT126
Manufacturer ON Semiconductor
File Size 128.11 KB
Description Noninverting Buffer / CMOS Logic Level Shifter
Datasheet download datasheet NL17SHT126 Datasheet
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Full PDF Text Transcription

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NL17SHT126 Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs The NL17SHT126 is a single gate noninverting 3−state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The NL17SHT126 requires the 3−state control input (OE) to be set Low to place the output into the high impedance state.
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