Datasheet4U Logo Datasheet4U.com

PDM31034 - Static RAM

Description

RAM organized as 131,072 x 8 bits.

Writing is accomplished when the write enable (WE) and the chip enable (CE) inputs are both LOW.

OE are both LOW.

Features

  • n High-speed access times Com’l: 9, 10, 12, 15 and 20 ns Ind’l. : 12, 15 and 20 ns Automotive: 15 and 20 ns n Low power operation (typical) - PDM31034SA Active: 200 mW Standby: 15 mW n Single +3.3V (±0.3V) power supply n TTL-compatible inputs and outputs n Packages Plastic SOJ (400 mil) - SO Plastic SOJ (300 mil) - TSO Plastic TSOP (II) - T.

📥 Download Datasheet

Datasheet preview – PDM31034

Datasheet Details

Part number PDM31034
Manufacturer PARADIGM
File Size 125.47 KB
Description Static RAM
Datasheet download datasheet PDM31034 Datasheet
Additional preview pages of the PDM31034 datasheet.

📁 Similar Datasheet

  • PDM1102H - MOSFET (Nihon Inter Electronics)
  • PDM1405HA - MOSFET MODULE Dual 140A/500V (Nihon Inter Electronics Corporation)
  • PDM41256 - 256K Static RAM 32K x 8-Bit (ETC)
  • PDM44018 - 64K x 18-Bit Fast CMOS SRAM (Paradigm Technology)
  • PDM44026 - 32K x 36-Bit Fast CMOS SRAM (Paradigm Technology)
  • PDM44028 - 64K x 18-Bit Fast CMOS SRAM (Paradigm Technology)
  • PDM44036 - 32K x 36-Bit Fast CMOS SRAM (Paradigm Technology)
  • PDM44038 - 64K x 18-Bit Fast CMOS SRAM (Paradigm Technology)
  • PDM44056 - 32K x 36-Bit Fast CMOS SRAM (Paradigm Technology)
  • PDM44058 - 64K x 18-Bit Fast CMOS SRAM (Paradigm Technology)
Other Datasheets by PARADIGM

Full PDF Text Transcription

Click to expand full text
Features n High-speed access times Com’l: 9, 10, 12, 15 and 20 ns Ind’l.: 12, 15 and 20 ns Automotive: 15 and 20 ns n Low power operation (typical) - PDM31034SA Active: 200 mW Standby: 15 mW n Single +3.3V (±0.3V) power supply n TTL-compatible inputs and outputs n Packages Plastic SOJ (400 mil) - SO Plastic SOJ (300 mil) - TSO Plastic TSOP (II) - T PRELIMINARY PDM31034 1 Megabit 3.3V Static RAM 1 128K x 8-Bit Revolutionary Pinout Description 2 The PDM31034 is a high-performance CMOS static RAM organized as 131,072 x 8 bits. Writing is accomplished when the write enable (WE) and the chip enable (CE) inputs are both LOW. Reading is 3 accomplished when WE remains HIGH and CE and OE are both LOW. The PDM31034 operates from a single +3.
Published: |