PM5381 Overview
Key Features
- Single chip ATM and POS User-Network Interface operating at 2488.32 Mbit/s
- Processes bit-serial 2488.32 Mbit/s STS-48 (STM-16-16c) data streams with on-chip clock and data recovery and clock synthesis
- Complies with Bellcore GR-253-CORE jitter tolerance, jitter transfer and intrinsic jitter criteria
- Provides termination for SONET Section, Line and Path overhead or SDH Regenerator Section, Multiplexer Section and High Order Path overhead
- Provides UTOPIA Level 3 32-bit wide System Interface (clocked up to 104 MHz) with parity support for ATM applications
- Provides SATURN POS-PHY Level 3รค 32-bit System Interface (clocked up to 104 MHz) for Packet over SONET (POS), or ATM applications
- Provides support for automatic protection switching via a 4-bit LVDS 777.76 MHz port
- Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes
- Provides a generic 16-bit microprocessor bus int
