FEATURES
Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 15/20/25/35 ns (Commercial/Industrial) – 15/20/25/35/45 ns (Military) Low Power Single 5V±10% Power Supply Output Enable & Chip Enable control functions Data Retention with 2.0V Supply Three-State Outputs TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350x550 mil LCC DESCRIPTION
Inputs and outputs are fully TTL-compatible. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. Access times as fast as 15 nanoseconds are available, permitting greatly enhanced syst
PYRAMID
