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P4C1299 - STATIC CMOS RAM

General Description

The P4C1299 and P4C1299L are a 262,144-bit ultra highspeed static RAM organized as 64K x 4.The CMOS memory requires no clock or refreshing and has equal access and cycle times.

Inputs and outputs are fully TTL-compatible.

The RAM operates from a single 5V±10% tolerance power supply.

Key Features

  • Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times).
  • 15/20/25/35 ns (Commercial/Industrial).
  • 15/20/25/35/45 ns (Military) Low Power Operation Single 5V±10% Power Supply Output Enable (OE) & Chip Enable (CE1 and CE2) Control Functions P4C1299/P4C1299L ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM Data Retention with 2.0V Supply (P4C1299L) Three-State Outputs TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved).

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Datasheet Details

Part number P4C1299
Manufacturer PYRAMID
File Size 718.82 KB
Description STATIC CMOS RAM
Datasheet download datasheet P4C1299 Datasheet

Full PDF Text Transcription for P4C1299 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for P4C1299. For precise diagrams, and layout, please refer to the original PDF.

FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 15/20/25/35 ns (Commercial/Industrial) – 15/20/25/35/45 ns (Military) Low Power Operation Single 5...

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ndustrial) – 15/20/25/35/45 ns (Military) Low Power Operation Single 5V±10% Power Supply Output Enable (OE) & Chip Enable (CE1 and CE2) Control Functions P4C1299/P4C1299L ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM Data Retention with 2.0V Supply (P4C1299L) Three-State Outputs TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350x550 mil LCC DESCRIPTION The P4C1299 and P4C1299L are a 262,144-bit ultra highspeed static RAM organized as 64K x 4.The CMOS memory requires no clock or refreshing and has equal access and cycle times. Inputs and outputs are ful

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