PYA28C010 Datasheet | PYRAMID

FEATURES Access Times of 120, 150, 200, and 250ns Single 5V±10% Power Supply Simple Byte and Page Write Low Power CMOS: - 60 m A Active Current - 500 µA Standby Current Fast Write Cycle Times 128K x 8 EEPROM Software Data Protection Fully TTL patible Inputs and Outputs Endurance: - 10,000 Cycles/byte - 100,000 Cycles/page Data Retention: 100 Years Available in the following package: - 32-Pin 600 mil Ceramic DIP - 32-Pin Ceramic LCC (450x550 mils) - 32-Pin Solder Seal Flatpack - 44-Pin Ceramic LCC (650x650 mils) DESCRIPTION The PYA28C010 is a 5 Volt 128Kx8 EEPROM using floating gate CMOS Technology. The device supports 64-byte page write operation. The PYA28C010 features DATA and Toggle Bit Polling as well as a system software scheme used to indicate early pletion of a Write Cycle. The device also includes user-optional software data protection. Data Retention is 100 Years. The device is available in a 32-Pin 600 mil wide Ceramic DIP, 32-Pin LCC, 32-Pin Solder Seal Flatpack and 44-Pin Ceramic LCC. Functional Block Diagram Pin Configuration Document # EEPROM103 REV 03 DIP (C10) LCC (L6) Revised July 2014 OPERATION - 128K x 8 EEPROM READ Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. WRITE Write operations are initiated when both CE and WE are LOW and OE is HIGH. The PYA28C010 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to pletion, typically within 5 ms. PAGE WRITE The page write feature of the AS28C010...