MN195001 Description
For munications Equipment MN195001 Single-Chip Fax Engine LSI Overview The MN195001 reduces to a single chip CPU functions related to facsimile control, peripheral device control functions, and modem functions. The last include plete fax/modem support for the ITU-T G3 remandations V.29, V.27ter, and V.21 Channels 1 and 2. The MN195001 consists of the following blocks:.
MN195001 Key Features
- Micro ROM: 4096 × 32 bits
- Data RAM: 512 × 16 bits × 2 sets
- Machine cycle: 90 ns
- Parallel multiplier: 16 bits × 16 bits × → 32 bits
- Arithmetic and logic unit (ALU): 32-bit Facsimile peripheral circuit block
- Scanner/plotter interface
- Two USART channels
- Two motor control channels
- One thermal head control channel
- Programmable chip select Analog circuit block