Overview: CCD Delay Line Series MN38662S
NTSC-patible CCD Video Signal Delay Element
Overview
The MN38662S is a CCD signal delay element for video signal processing applications. It contains such ponents as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 681 and 605 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits. When the switch input is "L" level, the MN38662S samples the input using the supplied clock signal with a frequency of three times the NTSC color signal subcarrier frequency (3.579545 MHz) and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. When the switch input is "H" level, the MN38662S disables the threefold-frequency circuit and samples the input with the image sensor drive frequency (9.53496 MHz or 9.545454 MHz) for the camera's 510 horizontal pixels and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Pin Assignment XIC VSS3 VDD3 VINC1 N.C.
