PI74ALVTC16374 Datasheet | Pericom Semiconductor

Features - The PI74ALVTC Family is designed for low voltage operation, VDD = 1.8V to 3.6V - Supports Live Insertion - 3.6V I/O Tolerant Inputs and Outputs - Bus Hold - High Drive, - 32/64m A @ 3.3V .. - Uses patented Noise Reduction Circuitry - Power-Off high impedance inputs and outputs - Industrial operation at - 40°C to +85°C - Packages available: - 48-pin 240 mil wide plastic TSSOP (A) - 48-pin 173 mil wide plastic SSOP (V) - 48-pin 300 mil wide plastic TVSOP (K) Product Description Peri Semiconductor’s PI74ALVTC series of logic circuits are produced in the pany’s advanced 0.35 micron CMOS technology, achieving industry leading speed. The PI74ALVTC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit Flip-Flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered Output Enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state in which the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup ponents. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to Vdd through a pullup resistor; the minimum value of the resistor is determined by the currentsinking capability of the driver. >C1 Logic Block Diagram 1OE 1CLK 1Q1 1D1 1D The family offers both I/O Tolerant, which allows it to operate in mixed 1.8/3.6V systems, and “Bus Hold,” which retains the data input’s last state whenever the data input goes to high-impedance,...