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PI90LVT386 - High-Speed Differential Line Receivers

General Description

The PI90LVx386 family consists of sixteen differential line receivers with 3-state outputs that implement Low-Voltage Differential Signaling (LVDS).

Key Features

  • Sixteen line receivers meet or exceed the requirements of the ANSI TIA/EIA-644-1995 Standard.
  • Designed for signaling rates up to 660 Mbps.
  • 0V to 3V common-mode input voltage range.
  • Operates from a single 3.3V supply.
  • Typical propagation delay time: 2.6ns.
  • Output skew 100ps (typical).
  • Part-to-part skew is less than 1ns.
  • Integrated 110-Ohm termination on PI90LVT386.
  • Low Voltage TTL (LVTTL) levels are 5V tolerant.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PI90LV386/PI90LVT386 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122 High-Speed Differential Line Receivers Features • Sixteen line receivers meet or exceed the requirements of the ANSI TIA/EIA-644-1995 Standard • Designed for signaling rates up to 660 Mbps • 0V to 3V common-mode input voltage range • Operates from a single 3.3V supply • Typical propagation delay time: 2.