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PI90LV02 - LVDS High-Speed Differential Line Receiver

General Description

The PI90LV02 and PI90LVT02 are single differential line receivers that use low-voltage differential signaling (LVDS) to support data rates up to 400 Mbps.

These products are designed for applications requiring high-speed, low-power consumption, low-noise generation, and a small package.

Key Features

  • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard.
  • Signaling rates up to 400 Mbps.
  • Interfaces to LVDS, LVPECL.
  • Bus-Terminal ESD exceeds 10kV.
  • Differential Input Voltage Threshold less than 100mV.
  • Typical Propagation Delay Times of 2.6ns.
  • Typical Power Dissipation of 40mW @200 MHz.
  • Low Voltage TTL (LVTTL) Level is 5V Tolerant.
  • Open-Circuit Fail Safe.
  • Output are High Impedance with VCC.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI90LV02/PI90LVT02 SOTinyTM LVDS High-Speed Differential Line Receiver Features • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard • Signaling rates up to 400 Mbps • Interfaces to LVDS, LVPECL • Bus-Terminal ESD exceeds 10kV • Differential Input Voltage Threshold less than 100mV • Typical Propagation Delay Times of 2.6ns • Typical Power Dissipation of 40mW @200 MHz • Low Voltage TTL (LVTTL) Level is 5V Tolerant • Open-Circuit Fail Safe • Output are High Impedance with VCC <1.