FEATURES
Two copies of CPU clock 100 MHz or 66.6 MHz operation Six copies of PCI clock, (synchronous with CPU clock) Two copies of REF clock @ 14.31818 MHz One copy of 48 MHz One copy of selectable 48/24 MHz Power management control input pins Isolated core VDD, VSS pins for noise reduction 28-pin SSOP (H) and TSSOP (L) packages 66 MHz 0.67% 1.35% 1.79% 100 MHz 0.65% 1.35% 1.79% DESCRIPTION
System clock frequencies of 66.6 MHz and 100 MHz are supported. Split supplies of 3.3V and 2.5V are used. 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required. An asynchronous PWR_DWN# signal may be used to orderly power down (or up) the system. CPU and PCI clocks may also be stopped by the CPU_STOP# and PCI_STOP# signals. The PI6C103 contains the Spread Spectrum function for only those clocks that synchronize to the CPU clocks (CPU and PCI clocks). SSC Options: Device PI6C103 PI6C103-05 PI6C103-06 Block Diagram XTAL_IN X...
Pericom Semiconductor
