FEATURES
ÎÎPCIe® 3.0/2.0/1.0 compliant àà PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.) ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ25MHz crystal or clock input frequency ÎÎHCSL outputs, 0.8V Current mode differential pair ÎÎJitter 35ps cycle-to-cycle (typ) ÎÎRMS phase jitter 12kHz ~ 20MHz @ 100MHz - 0.32ps (typ) ÎÎRMS phase jitter 12kHz ~ 20MHz @ 125MHz - 0.3ps (typ) ÎÎIndustrial temperature range ÎÎPackaging: (Pb-free and Green) àà 16-pin TSSOP (L16) DESCRIPTION
The device is used for PC or embedded systems. Using Pericom's patented Phase Locked Loop (PLL) techniques, the device takes a 25MHz crystal input and produces two pairs of differential outputs (HCSL) at 25MHz, 100MHz, 125MHz, 200MHz clock frequencies. Block Diagram Pin Configuration (16-Pin TSSOP) VDD S1:S0 2 X1/CLK 25 MHz crystal or clock X2 Pulling Capacitors Control Logic Crystal Driver Phase Lock Loop GND RR OE CLK0 CLK0 CLK1 CLK1 S0 S1 NC X1/CLK X2 OE GND NC 1 2 3 4 5 6 7 8 16 VDDX 15 CLK0 14 CLK0 13 GNDA 12 VDDA 11 CLK1 10 CLK1 9 IREF All trademarks are property of their respective owners.
Pericom Semiconductor
