FEATURES
ÎÎPCIe® 3.0/2.0/1.0 compliant àà PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.) ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V±5% and 2.5V±5% ÎÎ25MHz crystal or clock input frequency ÎÎHCSL outputs, 0.7V low power differential pair ÎÎJitter 35ps cycle-to-cycle (typ) ÎÎRMS phase jitter 12kHz ~ 20MHz @ 100MHz - 0.32ps (typ) ÎÎRMS phase jitter 12kHz ~ 20MHz @ 125MHz, 156.25MHz, 200MHz - 0.3ps (typ) ÎÎIndustrial temperature range ÎÎPackaging: (Pb-free and Green) àà 20-pin TSSOP (L20) DESCRIPTION
Using Pericom's patented Phase Locked Loop (PLL) techniques, the device takes a 25MHz crystal input and produces four pairs of differential outputs (HCSL) at 156.25MHz, 100MHz, 125MHz, 133.33MHz and 200MHz clock frequencies. Block Diagram Pin Configuration (20-Pin TSSOP) S[1:0] 2 XTAL_IN/CLK 25 MHz crystal or clock XTAL_OUT Pulling Capacitors VDDX Control Logic Crystal Driver GNDX VDDOA Phase Lock Loop OE0&1 Q0+ Q0Q1+ Q1Q2+ Q2Q3+ Q3OE GNDOA VSWING_CTRL VDDX OE0&1 S0 S1 XTAL_IN/ C...
Pericom Semiconductor
