FEATURES
ÎÎTwo differential LVPECL output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 62.5MHz, 125MHz, 156.25MHz ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.14ps (typical) ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal (12kHz – 20MHz): 0.3ps (typical) ÎÎFull 3.3V or 2.5V supply modes ÎÎIndustrial operating temperature ÎÎAvailable in lead-free package: 20-TSSOP DESCRIPTION
Using a 25MHz crystal, the most popular Ethernet frequencies can be generated based on the settings of 2 frequency select pins. APPLICATIONS
ÎÎNetworking systems Block Diagram XTAL_IN XTAL_OUT Ref_IN IN_SEL OSC M_reset PFD VCO M PLL_ByPass N_SEL[0:1] /N CLK0 CLK0# CLK1 CLK1# 15-0107 1 PI6LC48P0201 Rev. D 08/05/15 Pin Configuration - TSSOP NC VDDO CLK0 CLK0# M_reset PLL_ByPass NC VDDA N_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 VDDO 19 CLK1 18 CLK1# 17 GND 16 VDD 15 IN_SEL 14 Ref_IN 13 XTAL_IN 12 XTAL_OUT 11 N_SEL1 PI6LC48P0201 2-Output LVPECL Networking Clock Generator Pinout Table - TSSOP Pin No.