FEATURES
ÎÎTwo differential LVPECL output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 62.5MHz, 125MHz, 156.25MHz ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal (12kHz – 20MHz): 0.3ps (typical) ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal (12kHz – 20MHz): 0.5ps (max.) ÎÎFull 3.3V or 2.5V supply modes ÎÎIndustrial operating temperature ÎÎAvailable in lead-free package: 20-TQFN DESCRIPTION
Using a 25MHz crystal, the most popular Ethernet frequencies can be generated based on the settings of 2 frequency select pins. APPLICATIONS
ÎÎNetworking systems Block Diagram XTAL_IN XTAL_OUT Ref_IN IN_SEL OSC M_reset PFD VCO M PLL_ByPass N_SEL[0:1] /N CLK0 CLK0# CLK1 CLK1# 15-0103 1 PI6LC48P0201A Rev A 8/04/2015 Pin Configuration VDDO GND CLK0 CLK0# M_reset GND PLL_ByPass GND VDDA N_SEL0 1 2 3 4 20 19 18 17 5 GND 16 6 15 7 14 8 13 9 12 10 11 VDDO CLK1 CLK1# VDD IN_SEL Ref_IN XTAL_IN XTAL_OUT PI6LC48P0201A 2-Output LVPECL Networking Clock Generator VDD N_SEL1 Pinout Table Pin No.