PLL102-10 Overview
The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL.
PLL102-10 Key Features
- Zero input
- output delay
- Less than 700 ps device
- device skew
- Less than 250 ps skew between outputs
- Less than 100 ps cycle
- cycle jitter
- 2.5V or 3.3V power supply operation
- Available in 8-Pin SOIC or MSOP package