PLL102-10 Overview
Description
The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input.
Key Features
- output delay
- Less than 700 ps device
- Less than 250 ps skew between outputs
- Less than 100 ps cycle
- cycle jitter
