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PLL102-10 Datasheet

Low Skew Output Buffer

Manufacturer: PhaseLink Corporation

PLL102-10 Overview

The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL.

PLL102-10 Key Features

  • Zero input
  • output delay
  • Less than 700 ps device
  • device skew
  • Less than 250 ps skew between outputs
  • Less than 100 ps cycle
  • cycle jitter
  • 2.5V or 3.3V power supply operation
  • Available in 8-Pin SOIC or MSOP package

More Datasheets from PhaseLink Corporation

See all PhaseLink Corporation datasheets

Part Number Description
PLL102-108 Programmable DDR Zero Delay Clock Driver
PLL102-109 Programmable DDR Zero Delay Clock Driver
PLL102-15 Low Skew Output Buffer
PLL102-03 Low Skew Output Buffer
PLL102-04 Low Skew Output Buffer
PLL102-05 Low Skew Output Buffer
PLL103-01 Low Skew Buffer
PLL103-02 DDR SDRAM Buffer
PLL103-03 DDR SDRAM Buffer
PLL103-04 1-to-4 Clock Distribution Buffer

PLL102-10 Distributor