PLL520-17 Datasheet | PhaseLink Corporation

FEATURES - - - - - - - 65MHz to 130MHz Fundamental Mode Crystal. Output range: 65MHz - 800MHz (selectable 1x, 2x, 4x and 8x multipliers). Low Injection Power for crystal 50u W. Available outputs: PECL, LVDS, or CMOS. Integrated variable capacitors. Supports 3.3V-Power Supply. Available in 16 pin (TSSOP or SOIC) VDD XIN XOUT SEL3^ SEL2^ OE VCON GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GND CLKC VDD CLKT GND GND PLL 520-1x DESCRIPTION The PLL520-17/-18/-19 family of VCXO IC’s is specifically designed to pull high frequency fundamental crystals. They achieve very low current into the crystal resulting in better overall stability. Their internal varicaps allow an on chip frequency pulling, controlled by the VCON input. ^: Internal pull-up OUTPUT ENABLE LOGICAL LEVELS Part # PLL520-18 PLL520-17 PLL520-19 OE 0 (Default) 1 0 1 (Default) State Output enabled Tri-state Tri-state Output enabled BLOCK DIAGRAM OE input: Logical states defined by PECL levels for PLL520-18 Logical states defined by CMOS levels for PLL520-17/-19 SEL OE VCON XIN XOUT Oscillator Amplifier w/ integrated varicaps PLL (Phase Locked Loop) PLL by-pass PLL520-17/-18/-19 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 .phaselink. Rev 09/20/04 Page 1 PLL520-17/-18/-19 .. Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal) PIN DESCRIPTIONS Name XIN XOUT OE VCON GND CLKT CLKC SEL VDD Number 2 3 6 7 8,9, 10, 14 11 13 4,5,15,16 1, 12 Type I I I I P O O I P Description Crystal input. See Crystal Specification on page 3. Crystal output. See Crystal Specification on page 3. Output enable. See Output Enable Logic Levels on page 1. Voltage control input. Ground. True output PECL (PLL520-18) or LVDS (PLL520-19). No Connect for CMOS (PLL520-17). plementary output PECL (PLL520-18) or LVDS (PLL520-19). CMOS output for (PLL520-17). Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not...