PLL520-30 Description
Preliminary .. PLL520-30 PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) DIE CONFIGURATION 65 mil 25 26 24 23 22 21 20 19 18 17.
PLL520-30 Key Features
- 65MHz to 130MHz Fundamental Mode Crystal. Output range: 65MHz
- 130MHz (no PLL). Low Injection Power for crystal 50uW. plementary outputs: PECL or LVDS. Selectable OE Logic Integrated