PLL520-80
PLL520-80 is Low Phase Noise VCXO manufactured by PhaseLink Corporation.
..
Low Phase Noise VCXO (9.5-65MHz)
DIE CONFIGURATION
OUTSEL0^
65 mil
Features
- -
- -
- -
- - 19MHz to 65MHz fundamental crystal input. Output range: 9.5MHz
- 65MHz plementary outputs: PECL or LVDS output. Selectable OE Logic (enable high or enable low). Available outputs: PECL, LVDS, or CMOS (High Drive (30m A) or Standard Drive (10m A) output). Integrated variable capacitors. Supports 2.5V or 3.3V Power Supply. Available in die form.
OUTSEL1^
Reserved
N/C
(1550,1475)
17 16
GNDBUF CMOS LVDSB PECLB VDDBUF VDDBUF PECL LVDS OE_SEL^
XIN XOUT N/C
62 mil
Die ID: A2020-20C
S2^ OE CTRL VCON
DESCRIPTION The PLL520-80 is a VCXO IC specifically designed to work with fundamental crystals between 19MHz and 65MHz. The selectable divide by two feature extends the operation range from 9.5MHz to 65MHz. It requires very low current into the crystal resulting in better overall stability. The OE logic feature allows selection of enable high or enable low. Furthermore, it provides selectable CMOS, PECL or LVDS outputs.
11 30
C502A
31 1 2 3 4 5 6 7 8
10 9
Reserved
(0,0)
OUTPUT SELECTION AND ENABLE
OUT_SEL1- (Pad 18) 0 0 1 1 OE_SELECT (Pad 9) 0 OUT_SEL0- (Pad 25) 0 1 0 1 OE_CTRL (Pad 30) 0 1 (Default) 0 (Default) 1 Selected Output- High Drive CMOS Standard CMOS LVDS PECL (default) State Tri-state Output enabled Output enabled...
