The following content is an automatically extracted verbatim text
from the original manufacturer datasheet and is provided for reference purposes only.
View original datasheet text
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with
30 Ω termination resistors; 3-state
Rev. 02 — 11 August 2005
Product data sheet
1. General description
The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity.
The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems.
The registers are fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the flip-flop.
74ALVT162823 Datasheet
