74ALVT162823 Overview
The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity. The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. The registers are fully...
74ALVT162823 Key Features
- Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
- 5 V I/O patible
- Ideal where high speed, light loading or increased fan-in are required with MOS
- Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
- Live insertion and extraction permitted
- Power-up 3-state
- Power-up reset
- Output capability: +12 mA to -12 mA
- Outputs include series resistance of 30 Ω making external termination resistors
- Latch-up protection
74ALVT162823 Applications
- Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
