74F20 Datasheet PDF

DESCRIPTION

14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F20N N74F20D PKG DWG # SOT27-1 D0c D0d Q0 GND SF00065 SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS Dna, Dnb, Dnc, Dnd Q0, Q1 Data inputs Data outputs

DESCRIPTION

74F (U.L.) HIGH/LOW 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC DIAGRAM D0a D0b D0c D0d 1 2 6 4 5 Q0 FUNCTION TABLE INPUTS Dna L X X 9 10 8 12 13 Q1 OUTPUT Dnd X X X L H Qn H H H H L X X L X H Dnb X L X X Dnc X D1a D1b D1c VCC = Pin 14 GND = Pin 7 D1d H H NOTES: H = High voltage level L = Low voltage level X = Don’t care SF00066 LOGIC SYMBOL 1 2 4 5 9 10 12 13 IEC/IEEE SYMBOL 1 2 & 6 D0a D0b D0c D0d D1a D1b D1c D1d 4 5 Q0 Q1 VCC = Pin 14 GND = Pin 7 6 8 9 SF00067 10 8 12 13 SF00068 March 3, 1989 2 853–0332 95935 Philips Semiconductors Product specification Dual 4-input NAND gate 74F20

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device.