74F280B Datasheet | Philips Semiconductors

FEATURES - High-impedance NPN base inputs for reduced loading (20µA in Low and High states) PIN CONFIGURATION I6 I7 NC I8 ΣE ΣO GND 1 2 3 4 5 6 7 14 VCC 13 I5 12 I4 11 I3 - Buffered inputs - one normalized load - Word length easily expanded by cascading - Industrial temperature range available (- 40°C to +85°C) DESCRIPTION The 74F280B is a 9-bit Parity Generator or Checker monly used to detect errors in high speed data transmission or data retrieval systems. Both Even (∑E) and Odd (∑O) parity outputs are available for generating or checking even or odd parity on up to 9 bits. The Even (∑E) parity output is High when an even number of Data inputs (I0 - I8) are High. The Odd (∑O) parity output is High when an odd number of Data inputs are High. Expansion to larger word sizes is acplished by tying the Even (∑E) outputs of up to nine parallel devices to the data inputs of the final stage. This expansion scheme allows an 81-bit data word to be checked in less than 20ns. TYPE 74F280B 10 I2 9 8 I1 I0 SF00849 TYPICAL PROPAGATION DELAY 5.5ns TYPICAL SUPPLY CURRENT (TOTAL) 26m A ORDERING INFORMATION DESCRIPTION 14-pin plastic DIP 14-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F280BN N74F280BD INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = - 40°C to +85°C I74F280BN I74F280BD PKG. DWG. # SOT27-1 SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS I0 - I8 ∑E , ∑O DESCRIPTION Data inputs Parity outputs 74F(U.L.) HIGH/LOW 1.0/0.033 50/33 LOAD VALUE HIGH/LOW 20µA/20µA 1.0m A/20m A NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6m A in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL 10 11 12 13 8 9 2K I0 I1 I2 I3 I4...