74F595 Datasheet | Philips Semiconductors

FEATURES - Low noise, now switching feedthrough current - Controlled output edge rates - High impedance PNP base inputs for reduced loading (20µA in High and Low states) PIN CONFIGURATION Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q0 DS OE STCP SHCP SHR QS - 8-bit serial-in, parallel-out shift register with storage - 3-state outputs - Shift register has direct clear - Guaranteed shift frequency-DC to 100MHz DESCRIPTION The 74F595 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-State outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct overriding clear, serial input and serial output pins for cascading. Both the shift register and storage register clocks are positive edge-triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register. This device uses patented circuitry to control system noise and internal ground bounce. This is done by eliminating switching feedthrough current and controlling both Low-to-High and High-to-Low slew rates. TYPE 74F595 SF01096 TYPICAL f MAX 130MHz TYPICAL SUPPLY CURRENT (TOTAL) 65m A ORDERING INFORMATION DESCRIPTION 16-pin plastic DIP 16-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F595N N74F595D PKG DWG # SOT38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS Ds SHCP STCP SHR OE Qs Q0- Q7 Serial data input Shift register clock pulse input (active rising edge) Storage register clock pulse input (active rising edge) Shift register reset input (active Low) Output Enable input (active Low) Serial expansion output Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 50/33 150/40 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 1.0m A/20m A 3.0m A/24m A NOTE: One (1.0) FAST unit...