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74F597 - 8-Bit Shift Register

Description

The 74F597 consists of an 8-bit storage register feeding a parallel-in/serial-in, serial-out 8-bit shift register.

The storage register and shift register have separate positive edge triggered clocks.

The shift register has asynchronous reset and when SHCP is Low, it has asynchronous load.

Features

  • High impedance PNP base inputs for reduced loading (20µA in High and Low states) PIN.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS 74F597 8-bit shift register with input storage registers Product specification IC15 Data Handbook 1991 Sep 13 Philips Semiconductors Philips Semiconductors Product specification 8-bit shift register with input storage registers 74F597 FEATURES • High impedance PNP base inputs for reduced loading (20µA in High and Low states) PIN CONFIGURATION D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 16 VCC 15 D0 14 DS 13 SHLD 12 STCP 11 SHCP 10 SHRST 9 QS • 8-bit parallel storage register • 3-State output buffers • Shift register has asynchronous direct overriding reset • Shift load SHLD is functional when SHCP is Low and locked out when SHCP is High • Guaranteed shift frequency DC to 105MHz DESCRIPTION The 74F597 consists of an 8-bit storage register feeding a parallel-in/se
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