74F597 Datasheet | Philips Semiconductors

FEATURES - High impedance PNP base inputs for reduced loading (20µA in High and Low states) PIN CONFIGURATION D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 16 VCC 15 D0 14 DS 13 SHLD 12 STCP 11 SHCP 10 SHRST 9 QS - 8-bit parallel storage register - 3-State output buffers - Shift register has asynchronous direct overriding reset - Shift load SHLD is functional when SHCP is Low and locked out when SHCP is High - Guaranteed shift frequency DC to 105MHz DESCRIPTION The 74F597 consists of an 8-bit storage register feeding a parallel-in/serial-in, serial-out 8-bit shift register. The storage register and shift register have separate positive edge triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asynchronous load. The shift register load function has been modified to load when both SHLD and SHCP are Low. When SHCP is High the shift register load operation is not performed. Data will be properly shifted on the rising edge of SHCP when SHLD is High. SF00366 TYPE 74F597 TYPICAL f MAX 135MHz TYPICAL SUPPLY CURRENT (TOTAL) 42m A ORDERING INFORMATION DESCRIPTION 16-pin plastic DIP 16-pin plastic SO MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F597N N74F597D PKG DWG # SOT38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS Ds D0- D7 SHCP STCP SHLD SHRST Qs Serial data input Parallel data inputs Shift register clock pulse input Storage register clock pulse input Shift register load input (active Low) Shift register reset input (active Low) Serial data output DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 50/33 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 1.0m A/20m A NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6m A in the Low state. 1991 Sep 13 853- 1556 03964 Philips Semiconductors Product specification 8-bit shift register with input storage registers LOGIC SYMBOL 14 15 1 2 3 4 5 6 7 IEC/IEEE...