74F765-1 Datasheet | Philips Semiconductors

FEATURES - Allows two microprocessors to access the same bank of dynamic - Performs arbitration, signal timing, address multiplexing and refresh DESCRIPTION The 74F764-1/765-1 DRAM Dual-ported Controller is a high-speed synchronous dual-port arbiter and timing generator that allows two microprocessors, microcontrollers, or any other memory accessing device to share the same block of DRAM. The device performs arbitration, signal timing, address multiplexing, and refresh address generation, replacing up to 25 discrete devices. - 9 Address output pins allow direct control of up to 256K dynamic RAMs - External address multiplexing enables control of 1Mbit (or greater) dynamic RAMs 74F764-1 vs. 74F765-1 The 74F764-1, though functionally and pin-to-pin patible with the 74F765-1, differs from the later in that it has an on-chip address input latch. This is useful in systems that have unlatched or multiplexed address and data bus. The specialized outputs eliminate the need for signal terminations in essentially all applications. Both devices are available in 40-pin plastic DIP or 44-pin PLCC with pinouts designed to allow convenient placement of microprocessors, DRAMs, and other support chips. - Separate refresh clock allows adjustable refresh timing - 74F764-1 has an on-chip 18-bit address input latch - 74F764-1/765-1 allow control of dynamic RAMs with row access times down to 40ns - 74F764-1/765-1 output drivers designed for first reflected wave switching ORDERING INFORMATION DESCRIPTION 40-Pin Plastic Dual In-line Package 44-Pin Plastic Leaded Chip Carrier MERCIAL RANGE VCC = 5V±10%, Tamb = 0°C to 70°C 74F764-1N, 74F765-1N 74F764-1A, 74F765-1A DRAWING NUMBER SOT129- 1 SOT187- 2 PIN CONFIGURATIONS N Package A1 A10 A2 A11 A3 A12 A4 A13 A5 1 2 3 4 5 6 7 8 9 40 RCP 39 WG 38 GNT 37 CASEN 36 DTACK 35 RAS 34 MA0 33 MA1 32 MA2 31 GND 30 MA3 29 MA4 28 MA5 27 MA6 26 MA7 25 MA8 24 CP 23 SEL2 22 REQ2 21 REQ1 A4 7 A13 8 A5 9 A14 10 VCC 11 A6 12 A15 13 A7 14 A16 15 A8 16...