Description
The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity.
Features
- flip-flops.
- High speed parallel registers with positive edge-triggered D-type.
- High performance bus interface buffering for wide data/address
paths or busses carrying parity.
- High impedance PNP base inputs for reduced loading (20µA in
high and low states).
- IIL is 20µA vs 1000µA for AM29821 series.
- Buffered control inputs to reduce AC effects.
- Ideal where high speed, light loading, or increased fan-in as
required with MOS microprocessor.
74F826 Datasheet
