Philips 74HC174
The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.| Part No. | 74HC174 |
|---|---|
| Datasheet | 74HC174 Download |
| Manufacturer |  Philips |
| Description | Hex D-type flip-flop |
| Buy | Stock & Price |
FEATURES
● Six edge-triggered D-type flip-flops● Asynchronous master reset
● Output capability: standard
● ICC category: MSI
GENERAL DESCRIPTION
7A. 74HC/HCT174 The 74HC/HCT174 have six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The register is fully edge-triggered. The state of each D input, one set-up time prior to the LOW-to-HIGH clock transition, is transferred to the corresponding output of the flip-flop. A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements. QUICK REFERENCE DATA GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay CP to Qn MR to Qn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2.
