74HC174 Description
74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The mon clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output.
74HC174 Key Features
- Wide supply voltage range from 2.0 to 6.0 V
- CMOS low power dissipation
- High noise immunity
- Input levels
- For 74HC174: CMOS level
- For 74HCT174: TTL level
- Six edge-triggered D-type flip-flops
- Asynchronous master reset
- plies with JEDEC standards
- JESD8C (2.7 V to 3.6 V)