74HC7404 Datasheet | Philips Semiconductors

Synchronous or asynchronous operation - 3-state outputs - 30 MHz (typical) shift-in and shift-out rates - Readily expandable in word and bit dimensions - Pinning arranged for easy board layout: input pins directly opposite output pins - Output capability: driver (8 m A) - ICC category: LSI. APPLICATIONS - High-speed disc or tape controller - munications buffer. GENERAL DESCRIPTION 74HC/HCT7404 The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in pliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. A higher data-rate can be obtained in applications where the status flags are not used (burst-mode). With separate controls for shift-in (SI) and shift-out (SO), reading and writing operations are pletely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR), an output enable input (OE) and flags. The data-in-ready (DIR) and data-out-ready (DOR) flags indicate the status of the device. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. TYP. SYMBOL t PHL/t PLH fmax CI CPD Note 1. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC - 1.5 V. ORDERING INFORMATION EXTENDED TYPE NUMBER 74HC/HCT7404N 74HC/HCT7404D PACKAGE PINS 18 20 PIN POSITION DIL SO20 MATERIAL plastic plastic CODE SOT102 SOT163A PARAMETER propagation delay SO, SI to DIR and DOR maximum clock frequency input capacitance power dissipation capacitance per package note 1 CONDITIONS HC CL = 15 p F; VCC = 5 V 15 30 3.5 475 HCT 17 30 3.5 490 ns MHz p F p F UNIT September 1993 Philips Semiconductors Product specification 5-Bit x 64-word FIFO register; 3-state PINNING (SOT102) SYMBOL OE DIR SI DO to D4 GND MR Q4 to Q0 DOR SO VCC PIN 1 2 3 9 10 11, 12, 13, 14, 15 16 17 18 DESCRIPTION output enable input (active LOW) data-in-ready output shift-in...