74HCT175 Datasheet | Philips Semiconductors

FEATURES - Four edge-triggered D flip-flops - Output capability: standard - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. 74HC/HCT175 The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q outputs. The mon clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All Qn outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where both the true and plement outputs are required and the clock and master reset are mon to all storage elements. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL t PHL PARAMETER propagation delay CP to Qn, Qn MR to Qn t PLH propagation delay CP to Qn, Qn MR to Qn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in p F VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 17 15 83 3.5 32 16 16 54 3.5 34 ns ns MHz p F p F CONDITIONS HC CL = 15 p F; VCC = 5 V 17 15 16 19 ns ns HCT UNIT 1998 Jul 08 Philips Semiconductors Product specification Quad D-type flip-flop with reset; positive-edge trigger ORDERING INFORMATION TYPE NUMBER 74HC175N; 74HCT175N 74HC175D; 74HCT175D 74HC175DB; 74HCT175DB 74HC175PW; 74HCT175PW PACKAGE NAME DIP16 SO16 SSOP16 TSSOP16 DESCRIPTION plastic dual...