Philips 74HCT175
The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.| Part No. | 74HCT175 |
|---|---|
| Datasheet | 74HCT175 Download |
| Manufacturer |  Philips |
| Description | Quad D-type flip-flop |
| Buy | Stock & Price |
FEATURES
● Four edge-triggered D flip-flops● Output capability: standard
● ICC category: MSI
GENERAL DESCRIPTION
7A. 74HC/HCT175 The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q outputs. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All Qn outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL PARAMETER propagation delay CP to Qn, Qn MR to Qn tPLH propagation delay CP to Qn, Qn MR to Qn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2.
