Nexperia 74HCT175
74HCT175 is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn) and complementary outputs (Qn and Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.| Part No. | 74HCT175 |
|---|---|
| Datasheet | 74HCT175 Download |
| Manufacturer |  Nexperia |
| Description | Quad D-type flip-flop |
| Buy | Stock & Price |
FEATURES AND BENEFITS
● Input levels:● For 74HC175: CMOS level
● For 74HCT175: TTL level
● Four edge-triggered D-type flip-flops
● Asynchronous master reset
● Complies with JEDEC standard no. 7A
● ESD protection:
● HBM JESD22-A114F exceeds 2000 V
● MM JESD22-A115-A exceeds 200 V
● Specified from -40 °C to +85 °C and -40 °C to +125 °C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC175D -40 °C to +125 °C SO16 74HCT175D 74HC175PW -40 °C to +125 °C TSSOP16 74HCT175PW
DESCRIPTION
plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT403-1 Nexperia 74HC175; 74HCT175 Quad D-type flip-flop with reset; positive-edge trigger 4. Functional diagram 9 4 CP Q0 D0 Q0 2 3 5 D1 Q1 7 Q1 6 12 D2 Q2 10 11 Q2 13 Q3 D3 MR Q3 15 14 1 aaa-008921 Fig. 1. Logic symbol D0 D1 9 C1 1R 4 1D 5 12 13 Fig. 2. IEC logic symbol D2 D3 2 3 7 6 10 11 15 14 aaa-008922 CP MR Fig.
