74HCT173 Datasheet | Philips Semiconductors

FEATURES - Gated input enable for hold (do nothing) mode - Gated output enable control - Edge-triggered D-type register - Asynchronous master reset - Output capability: bus driver - ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (Q0 to Q3) and master reset (MR). When the two data enable inputs (E1 and E2) are LOW, the data on the Dn inputs is loaded into the register QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT173 synchronously with the LOW-to-HIGH clock (CP) transition. When one or both En inputs are HIGH one set-up time prior to the LOW-to-HIGH clock transition, the register will retain the previous data. Data inputs and clock enable inputs are fully edge-triggered and must be stable only one set-up time prior to the LOW-to-HIGH clock transition. The master reset input (MR) is an active HIGH asynchronous input. When MR is HIGH, all four flip-flops are reset (cleared) independently of any other input condition. The 3-state output buffers are controlled by a 2-input NOR gate. When both output enable inputs (OE1 and OE2) are LOW, the data in the register is presented to the Qn outputs. When one or both OEn inputs are HIGH, the outputs are forced to a high impedance OFF-state. The 3-state output buffers are pletely independent of the register operation; the OEn transition does not affect the clock and reset operations. TYPICAL SYMBOL t PHL/ t PLH PARAMETER propagation delay CP to Qn MR to Qn maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 CONDITIONS HC CL = 15 p F; VCC = 5 V 17 13 88 3.5 20 17 17 88 3.5 20 ns ns MHz p F p F HCT UNIT fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 ×...